CHIP SCALE PACKAGE AND METHOD FOR MARKING CHIP SCALE PACKAGES

摘要

A method for marking chip scale packages at the wafer level is provided. First, a positioning step is performed to determine the position of a plurality of semi-finished chip scale packages formed on a wafer. Each of the semi-finished chip scale package includes a plurality of terminals for making external electrical connections and each die has a plurality of bonding pads on an active surface thereof. The bonding pads are electrically connected to the respective terminals wherein a backside surface of the die is exposed from a surface of the respective semi-finished chip scale package. The exposed backside surface of the die is then marked by ink-jet printing. Afterward, the ink marks on the dice are cured. Finally, the wafer is diced to obtain a plurality of separated chip scale packages.