SAMPLING SWITCH AND PIPELINE A/D CONVERTER

摘要

A boot strap sampling switch has a capacitor C1 for charging a VDD-VSS voltage and a capacitor C3 for charging zero charges during a hold period. During a sampling period, the capacitor C1 and the capacitor C3 are connected in parallel and this parallel circuit is connected between an analog input terminal Vin and the control terminal of an electric control switch (M1) consisting of an MOS transistor. Capacitance ratio between the capacitor C1 and the capacitor C3 is set to such a capacitance ratio that the control voltage of the electric control switch (M1) is reduced to a voltage not exceeding the withstand voltage of a gate oxide film.Consequently, the withstand voltage of the gate oxide film in the electric control switch (M1) can be prevented from being exceeded by simply adding the capacitor C3 without causing an increase in power consumption or in the number of elements, and the electric control switch (M1) can be protected effectively.