| 摘要 |
Bit lines of a memory device are arranged by an interleaving of even and odd bit lines and segregated into an even and odd bank. A discharge network discharges the banks alternately. A bit line selection network alternately connects the banks to a sense amplifier. The bank of odd bit lines is discharged just prior to a selection of the bank of even bit lines for reading and vice-versa. Interleaving even and odd bit lines in combination with alternating selection and discharge of banks reduces a cross coupling voltage. A discharge delay ensures that a sense amplifier does not detect any signal during a discharge phase. The discharge delay is much shorter than the cross coupling delay required with no discharge scheme present. Discharging complementary banks of bit lines plus reduced discharge delay ensures that along with a short access time, correct data are detected by the sense amplifier.
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