| 摘要 |
<p>A semiconductor device and a manufacturing method thereof are provided to improve alignment and overlay accuracy by improving an asymmetric profile of an alignment key and an overlay vernier. A space region of an alignment key is divided into a plurality of line/space patterns with a fine line width. The line width of space pattern is 0.2 to 0.5 micrometers. A plurality of isolation type dummy patterns(185) having a rectangular shape are formed at both sides of the outermost space pattern(180). An overlay vernier of a box in box type includes a space region. The asymmetry of the overlay vernier is prevented by forming the isolation type dummy patterns.</p> |
