| 摘要 |
PROBLEM TO BE SOLVED: To facilitate design and improve reliability by a new circuit designing method using a verilog language. SOLUTION: In specifications condition setting (S10), an input condition 11 and an output condition 12 for a circuit are specified. The input condition 11 and the output condition 12 are described by a truth-value table 10 using a count value called a step for managing the entire conditions of the circuit. Next, in specifications circuit designing (S11), a truth-value table (input and output conditions) defined by specifications conditions are described in a verilog language as they are. In this verilog description 20, for example, contents of module declaration and input-output pin declaring part 21, an input-output defining part 22, an internal register declaring part 23, and a circuit operation description section are described. In other words, a design format for utilizing truth-value table in circuit description as it is used. Then, operation confirmation (S12) is performed according to the input-output conditions described in the verilog language, and when the operation confirmation is completed, the circuit is completed (S13). COPYRIGHT: (C)2008,JPO&INPIT
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