| 摘要 |
PROBLEM TO BE SOLVED: To provide a multiport memory access (MPMA) control module. SOLUTION: The MPMA control module is provided with a plurality of I/O ports respectively electrically connected to a plurality of prearranged external FIFO memories and a DRAM, wherein an I/O port has a packing/unpacking device, an internal FIFO memory and an address progressive counter, the packing/unpacking device adjusts the width of a data bus for reading/writing to be the same width as that of a DRAM control IP interface desired to be subjected to reading/writing, a FIFO memory is electrically connected to the packing/unpacking device, a difference between a user's interface and a clock drain of a memory is adjusted, the address progressive counter is electrically connected to the internal FIFO memory, and the plurality of I/O ports being an address generator of the DRAM with each of the I/O ports corresponding thereto are provided with the range of a memory address for respectively controlling the prearranged DRAM. COPYRIGHT: (C)2008,JPO&INPIT
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