| 摘要 |
A memory block of a semiconductor memory array where the semiconductor memory array is a NOR array, a NAND array, or an AND array includes a bit line, memory cells where each memory cell has a floating gate including a charge trapping layer containing silicon and nitrogen, a metal-oxide-semiconductor select transistor that separates said bit line and said memory cells, a semiconductor region enclosed within the drain of said select transistor with a conductivity type that is opposite to that of said drain, and a semiconductor well region shared by said select transistor and said memory cells.
|
