| 摘要 |
In one embodiment, a method for crosstalk-aware timing analysis includes accessing a design of a circuit and identifying critical paths in the design. Each critical path includes one or more victim interconnects and one or more cells. The method includes identifying potential aggressor interconnects associated with each victim interconnect and, for each victim interconnect, extracting parasitics of the victim interconnect and the potential aggressor interconnects associated with the victim interconnect. The method includes computing timing windows of the potential aggressor interconnects and computing a first timing of each cell and each victim interconnect on each critical path. The method also includes, for each critical path, generating timing waveforms of the potential aggressor interconnects, traversing the critical path from a start point on the critical path to an end point on the critical path, and, computing a second timing of each cell and each victim interconnect on the critical path according to a traversal of the critical path.
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