STACKED DIE SEMICONDUCTOR DEVICE

摘要

A STACKED MULTICHIP PACKAGE (100) HAS A BASE CARRIER (102) HAVING A TOP SIDE (108) AND A BOTTOM SIDE (110), A BOTTOM INTEGRATED CIRCUIT DIE (104) HAVING A BOTTOM SURFACE (112) ATTACHED TO THE BASE CARRIER TOP SIDE (108), AND AN OPPOSING, TOP SURFACE (114). THE TOP SURFACE (114) HAS A PERIPHERAL AREA INCLUDING A PLURALITY OF FIRST BONDING PADS AND A CENTRAL AREA (120). A BEAD (124) IS FORMED ON THE TOP SURFACE (114) OF THE BOTTOM DIE (104) BETWEEN THE PERIPHERAL AREA AND THE CENTRAL AREA (120). A TOP INTEGRATED CIRCUIT DIE (106) HAVING A BOTTOM SURFACE IS POSITIONED OVER THE BOTTOM DIE (104) AND THE BOTTOM SURFACE OF THE TOP DIE (106) IS ATTACHED TO THE TOP SURFACE (114) OF THE BOTTOM DIE (104) VIA THE BEAD (124). THE BEAD (124) MAINTAINS A PREDETERMINED SPACING BETWEEN THE BOTTOM DIE (104) AND THE TOP DIE (106) SO THAT WIREBONDS OF FIRST WIRES (122) CONNECTING THE BOTTOM DIE (104) TO THE BASE CARRIER (102) ARE NOT DAMAGED WHEN THE TOP DIE (106) IS ATTACHED TO THE BOTTOM DIE (104).FIG.3