| 摘要 |
<p>Bit lines (19) in a memory array (12) are configured by a select switch matrix (25) to apply the same VD voltage to two adjacent bit lines (33a, 33b) on the drain side of a selected memory cell (75) for the purpose of blocking charge leakage through the cell (76) adjacent to the selected or addressed cell. The switch matrix (25) features transistors with electrodes connected to bit line segments (19) while control electrodes are connected to control lines (27) from a select decoder (29). The switch matrix (25) communicates with address decoders (21 and 23) for setting switches needed to configure the bit lines as needed with the charge leakage blocking voltage.</p> |
