发明名称 |
Methods of Forming CMOS Integrated Circuits Using Gate Sidewall Spacer Reduction Techniques |
摘要 |
Methods of forming field effect transistors include methods of forming PMOS and NMOS transistors by forming first and second gate electrodes on a substrate and then forming an electrically insulating layer having etch-enhancing impurities therein, on the first and second gate electrodes. The electrically insulating layer may be formed as a boron-doped silicon nitride layer or an electrically insulating layer that is doped with germanium and/or fluorine. The electrically insulating layer is etched-back to define first sidewall spacers on the first gate electrode and second sidewall spacers on the second gate electrode. P-type source and drain region dopants are then implanted into the semiconductor substrate, using the first sidewall spacers as a first implant mask. The second sidewall spacers on the second gate electrode are then etched back to reduce their lateral dimensions. N-type source and drain region dopants are then implanted into the semiconductor substrate, using the second sidewall spacers with reduced lateral dimensions as a second implant mask.
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申请公布号 |
US2008124859(A1) |
申请公布日期 |
2008.05.29 |
申请号 |
US20060563476 |
申请日期 |
2006.11.27 |
申请人 |
SUN MIN CHUL;YANG JONG HO;KO YOUNG GUN;KU JA HUM;PARK JAE EON;YANG JEONG HWAN;BAIOCCO CHRISTOPHER VINCENT;LEAKE GERALD |
发明人 |
SUN MIN CHUL;YANG JONG HO;KO YOUNG GUN;KU JA HUM;PARK JAE EON;YANG JEONG HWAN;BAIOCCO CHRISTOPHER VINCENT;LEAKE GERALD |
分类号 |
H01L21/8238;H01L21/336 |
主分类号 |
H01L21/8238 |
代理机构 |
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