发明名称 |
Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs by preprocessing |
摘要 |
Preprocessing parallel sequences of "wait" statements and synthesizing these multiple "wait" statements to construct support for RTL tools. This is accomplished by preprocessing a VHDL process with multiple wait statements (referred to as BehFSM) into an equivalent register transfer
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申请公布号 |
US2008127126(A1) |
申请公布日期 |
2008.05.29 |
申请号 |
US20060522036 |
申请日期 |
2006.09.16 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DRASNY GABOR;BOBOK GABOR;EL-ZEIN ALI |
分类号 |
G06F9/45 |
主分类号 |
G06F9/45 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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