| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a sufficient margin to variations in an input waveform. <P>SOLUTION: For example, there are provided: a clock data determination circuit CD_JGE for receiving an input data signal DIN and a clock signal CLK to output a reproduction data signal DATA and phase comparison signals EARLY, LATE; and a clock signal generation circuit CLK_GEN generating the CLK, where a phase is corrected based on EARLY, LATE. The CD_JGE latches DIN with a plurality of thresholds as criteria in synchronization with CLK, and processes the latched results to generate two kinds of candidates comprising the combination of the reproduction data and phase comparison signals. A selector circuit SEL selects one of the two kinds of candidates based on the code of the reproduction data signal DATA of a previous cycle. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
