发明名称 Gradation potential generation circuit, data driver of display device and the display device
摘要 A gradation potential generation circuit includes a first ladder resistance circuit supplied with a first and a second reference voltages to both ends to generate j number of gradation potentials (j is an integer of 2 or more) and output the generated j number of gradation potentials to j number of first nodes, where the j number of gradation potentials being generated by dividing the first and the second reference voltages, a second ladder resistance circuit to generate k number of gradation potentials out of the j number of gradation potentials (where j>k) generated by the first ladder resistance circuit and k number of switches to supply the k number of gradation potentials generated by the second ladder resistance circuit to k number of first nodes out of the j number of first nodes according to a first control signal.
申请公布号 US2008122820(A1) 申请公布日期 2008.05.29
申请号 US20070979799 申请日期 2007.11.08
申请人 NEC ELECTRONICS CORPORATION 发明人 UMEDA KENGO;TSUCHI HIROSHI
分类号 G09G5/00 主分类号 G09G5/00
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