| 摘要 |
PROBLEM TO BE SOLVED: To provide a wiring structure reducing a line resistance variation. SOLUTION: A semiconductor device includes a region of closely packed lines and a region including an isolated line, separated by a region of carbon-doped silicon oxide film. As a surface of the semiconductor device is etched, an etching rate varies depending on an etched material. Cross-sectional area of the isolated line need to be adjusted to compensate for a slow etching process in that region, depending on the etching rate. The closely packed lines has a height a and a width b, thus having a cross-sectional area of a*b. However, the isolated line has a height D*a, and a width E*b, where D*E=1. One or more etching processes may be used, and the line width is adjusted depending on the etching processes. COPYRIGHT: (C)2008,JPO&INPIT |
