发明名称 SERIALIZER/DE-SERIALIZER BUS CONTROLLER INFERFACE
摘要 PROBLEM TO BE SOLVED: To provide systems and methods that enable improvements in ASIC testing. SOLUTION: An application-specific integrated circuit (ASIC) uses a dedicated interface between core logic and an independent serializer/de-serializer bus (SBus), to provide SBus capabilities to the core logic. In addition to the dedicated interface, the ASIC includes a controller that responds to a set of signals and a plurality of receivers distributed surrounding the SBus. Each of the receivers responds to a set of commands that can be reused to test logic and support functions across each revision of the ASIC, as well as, to test separate ASICs having similar configurations for support functions, without requiring the generation of a discrete scan vector that tests the ASIC. Additional interfaces, such as I.E.E.E. 1149.1 interface, further extend the SBus functionalities up to external test equipment. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008122374(A) 申请公布日期 2008.05.29
申请号 JP20070281782 申请日期 2007.10.30
申请人 AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PRIVATELTD 发明人 VOLZ AARON MATTHEW;VANDIVIER SUZETTE DENISE;SLAVICK JEFFREY ANDREW
分类号 G01R31/28 主分类号 G01R31/28
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