发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT FOR COMMUNICATION AND WIRELESS COMMUNICATION TERMINAL DEVICE USING THE SAME
摘要 <P>PROBLEM TO BE SOLVED: To avoid a transmission Tx-VCO 22 from covering a higher frequency of an RF reception signal in accordance with an FDD system when generating an RF test signal for reception error calibration for calibrating a reception error between an I phase signal and a Q phase signal output from demodulation signal processing circuits 5, 6, ..., 11, 12 connected to reception mixers 3, 4, and to avoid a malfunction in the reception error calibration when generating the RF test signal for reception error calibration. <P>SOLUTION: In a calibration mode of a reception error calibration circuit 13, an RF test signal generation unit 20 generates an RF test signal utilizing an oscillation output signal of the transmission Tx-VCO 22 and other circuits 23, 40, 42, 43 and supplies the RF test signal to the reception mixers 3, 4 via a switch 2. The RF test signal has a frequency within an RF reception frequency band of a higher frequency than a frequency of an RF transmission signal within a peak frequency band of multiband wireless frequency communication. In a reception mode, the switch 2 is changed over and an output of a low noise amplifier 1 which amplifies an RF reception signal of an antenna ANT, is supplied to the reception mixers 3, 4. <P>COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008124965(A) 申请公布日期 2008.05.29
申请号 JP20060308821 申请日期 2006.11.15
申请人 RENESAS TECHNOLOGY CORP 发明人 MAEDA KOJI;TANAKA SATOSHI;YAMAWAKI DAIZO;AKAMINE YUKINORI;ITO MASAHIRO
分类号 H04L27/38;H04B1/40;H04B1/707;H04B17/00;H04J13/00;H04L27/227 主分类号 H04L27/38
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