| 摘要 |
An array of flash memory cells arranged in a plurality of rows and a plurality of columns includes a first row comprising a plurality of units. Each unit includes a plurality of flash memory cells, an erase-gate line connecting erase-gates of all flash memory cells in the first row, a source line connecting source nodes of all flash memory cells in the first row, a word line connecting word-line nodes of all flash memory cells in the first row, and a local control-gate (CG) line connecting control-gates of flash memory cells only in the unit, wherein each local CG line is disconnected from remaining local CG lines in the first row. The array further includes bit-lines each connecting bit-line nodes of flash memory cells in a same column.
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