| 摘要 |
<p>The invention relates to an electronic circuit for extracting a clock signal from an incident binary data sequence incoming at a constant rate. The electronic circuit includes an oscillator (VCO) having a voltage-controlled frequency providing a sinusoidal signal, a circuit (R, Cp, RD, I1, I2) for extracting transitions fronts of the binary sequence and generating a short pulse at each transition, a sampler (MLT) for sampling the level of the sinusoidal voltage during the short impulse, and an integrator (AOP, R1, C1) for integrating this level during the successive impulses, the output of the integrator being applied as a control voltage to the frequency controlled oscillator, the output of the oscillator being the desired clock frequency with a closed-loop phase that crosses zero essentially at the middle of the interval between two binary data transitions. Such a circuit can be used in digital data transmission applications of the series-type, in which data are received without simultaneously receiving a clock signal.</p> |
