| 摘要 |
In semiconductor memory devices having hierarchical bit line structures, a transfer transistor provided between a main bit line and a sub-bit line hinders achievement of a high speed and a low voltage. A sub-bit line SBL in a subarray 12 is connected via a first transistor PC 1 to a power source voltage, and via a second transistor NC 1 to a ground voltage. A main bit line MBLj is connected via a third transistor PD 1 to the power source voltage. The gate electrodes of the first transistor PC 1 and the second transistor NC 1 are connected to the main bit line MBLj, the gate electrode of the third transistor PD 1 is connected to the sub-bit line SBL. In an initial state, a voltage of the main bit line MBLj is controlled to be at an H level, and voltages of word lines WLi 1 to Wlip are controlled to be at an L level. When a read operation is performed, the voltage of the main bit line MBLj transitions to the L level, and thereafter, the voltage of a selected word line transitions to the H level.
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