发明名称 Scheduling store-forwarding of back-to-back multi-channel packet fragments
摘要 Disclosed is an apparatus and method for an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments. The apparatus may include a data extraction block, a plurality of data assemblers, a scheduler, and an output memory. The scheduler may be configured to operate according to a scheduling policy. The scheduling policy may include a set of priorities to determine an order of scheduling writes to the output memory from a plurality of data assemblers. The scheduling policy may also include selecting one or more of the plurality of data assemblers having a fill level greater than twice an input data path width of an input data bus and having no end-of-packet (EOP) or start-of-packet (SOP) as a first priority, selecting one or more of the plurality of data assemblers having a fill level greater than twice the input data path width of the input data bus, and not covered in the first priority selection, as a second priority, selecting one or more of the plurality of data assemblers having a fill level greater than the input data path width of the input data bus, and not covered in the first and second priority selections, as a third priority, and selecting one or more of the plurality of data assemblers having an end-of-packet (EOP) as a fourth priority.
申请公布号 US7379467(B1) 申请公布日期 2008.05.27
申请号 US20040841774 申请日期 2004.05.06
申请人 CYPRESS SEMICONDUCTOR CORPORATION 发明人 PAUL SOMNATH;REKHI SANJAY
分类号 H04L12/28;H04J3/16;H04L12/56 主分类号 H04L12/28
代理机构 代理人
主权项
地址