| 摘要 |
A three-terminal snapback device is utilized with a control circuit to provide a low snapback voltage that is protected from non-ESD voltage spikes and ripples. In response to a fast edge, the control circuit lowers the snapback voltage, unless a status signal indicates that normal operating voltages are present, and raises the snapback voltage a predefined time later. If the fast edge represents an ESD pulse, SCR operation is initiated at the lowered snapback voltage. If the fast edge represents a power on sequence, the maximum voltage is less than the momentarily lowered snapback voltage and therefore insufficient to initiate SCR operation. Further, once normal operating voltages are present, the control circuit continuously maintains the raised snapback voltage so that a non-ESD voltage spike or ripple can not improperly turn on the snapback device.
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