发明名称 Packet processing system
摘要 Some embodiments relate to a processor to provide a plurality of execution threads, a local memory associated with the processor, and a content-addressable memory associated with the processor. An execution thread of the processor may determine an ordering queue, associate a current thread with a last position in the ordering queue, receive a queue release signal from a previous thread in the ordering queue, and execute a critical code segment associated with the ordering queue.
申请公布号 US7379460(B2) 申请公布日期 2008.05.27
申请号 US20030456460 申请日期 2003.06.06
申请人 INTEL CORPORATION 发明人 BALAKRISHNAN VINOD K.
分类号 H04L12/28;G06F3/00;G06F9/44;G06F9/46;G06F13/00;H04L12/56 主分类号 H04L12/28
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