| 摘要 |
An integrated circuit, such as a SRAM cell ( 130 ), including an inverted FinFET transistor (P 2 ) and a FinFET transistor (N 3 ). The inverted FinFET transistor includes a first gate region ( 108 ) formed by semiconductor structure ( 100 ) on a substrate, a first body region comprised of a semiconductor layer ( 104 ), having a first channel region ( 112 ) disposed on the first gate region and a source ( 110 ) and drain ( 114 ) formed on either side of the first channel region. The FinFET transistor (N 3 ) is coupled to the inverted FinFET transistor, and includes a second body region formed by the semiconductor structure ( 102 ), having a second channel region ( 118 ), and a source ( 116 ) and drain ( 120 ) formed on either side of the second channel region, and a second gate region ( 122 ) comprised of the semiconductor layer, disposed on the second channel region.
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