发明名称 Circuit and method for digital delay and circuits incorporating the same
摘要 A method includes generating multiple delayed versions of a first signal using at least one first delay line, selecting at least one version of the first signal, and generating a second signal based on the at least one selected version of the first signal. The method also includes generating multiple delayed versions of the second signal using at least one second delay line, and selecting at least one version of the second signal. In addition, the method includes modifying selection of the at least one version of the first signal and the at least one version of the second signal to achieve a desired output signal. This method could be used in various circuits, such as duty cycle correction circuits, frequency multiplier circuits, and digital multiphase oscillator circuits.
申请公布号 US7378893(B1) 申请公布日期 2008.05.27
申请号 US20060644476 申请日期 2006.12.22
申请人 NATIONAL SEMICONDUCTOR CORPORATION 发明人 KANG DAE WOON
分类号 G06F1/04 主分类号 G06F1/04
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