发明名称 WAFER LEVEL PACKAGE WITH DIE RECEIVING CAVITY AND METHOD OF THE SAME
摘要 A wafer level package with die receiving cavity and its method are provided to offer a FO-WLP(fan out-wafer level package) structure not having an RDL(re-distribution layer) for reducing a thickness of the package, and offer an excellent board level reliability test of temperature circulation. A substrate comprises a die receiving cavity formed within an upper surface of the substrate, and a through hole structure(6). A die is disposed within the die receiving cavity(4) by adhesion. A dielectric layer(18) is formed on the die and the substrate. An RDL(24) is formed on the dielectric layer, wherein the RDL is coupled to the die and a terminal pad through the through hole structure. Wherein a terminal pad is formed under the through hole structure and a conductive trace formed on a lower surface of the substrate.
申请公布号 KR20080046120(A) 申请公布日期 2008.05.26
申请号 KR20070118905 申请日期 2007.11.21
申请人 ADVANCED CHIP ENGINEERING TECHNOLOGY, INC. 发明人 YANG WEN KUN;CHANG JUI HSIEN
分类号 H01L23/12 主分类号 H01L23/12
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