| 摘要 |
An error detection circuit for a latch precharges two dynamic nodes whose discharge paths are gated by true and complement storage nodes of the latch, such that one and only one of the dynamic nodes always discharges when the clock signal transitions from an active state to an inactive state. If a soft error flips the contents of the latch during storage mode the other dynamic node will discharge. A gate having inputs coupled to the dynamic nodes produces an error signal when both nodes have discharged. The error signal can then be used to select between true and complement outputs of the latch. The invention can be implemented in a more robust embodiment which examines the outputs of two error detection circuits to generate a combined error signal that ensures against false error detection when an upset occurs within one of the detection circuits.
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