发明名称 LOOK-UP TABLE CASCADE CIRCUIT, LOOK-UP TABLE CASCADE ARRAY CIRCUIT AND A PIPELINE CONTROL METHOD THEREOF
摘要 A look-up table cascade circuit having N look-up tables connected in cascade for implementing a desired logic function, comprising: N memory cell arrays for storing data of the look-up table in memory cells; N input select circuits for selecting a word line and bit lines to specify memory cells based on an input variable to the look-up table; N output circuits for selectively coupling data in the memory cells selected by the input select circuit to an input/output path and for outputting the data as an output variable of the look-up table; and N-1 connection circuits arranged between each preceding output circuit and each subsequent input select circuit, for receiving an external input variable and the output variable output from each preceding output circuit, and for selectively distributing all or part of an external output variable and the input variable based on connection information.
申请公布号 US2008117710(A1) 申请公布日期 2008.05.22
申请号 US20070942278 申请日期 2007.11.19
申请人 ELPIDA MEMORY, INC. 发明人 KAJIGAYA KAZUHIKO
分类号 G11C8/00 主分类号 G11C8/00
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