| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce a circuit scale by saving the read access of a CPU interface part in an internal circuit of an ASIC, an FPGA or the like without generating bus collision. <P>SOLUTION: In the case of receiving a data write signal from a CPU (101) to AIC and FPGA devices (106) to (107), a CPU bus access auxiliary circuit (103) performs control for writing data output from the CPU in the address of the device pertinent to the address output from the CPU, and stores the written address and written data in an external RAM (105), and in the case of receiving a data read signal from the device from the CPU, the CPU bus access auxiliary circuit (103) reads the data stored in the address of the external RAM, and outputs the data to the CPU without performing access to the device. <P>COPYRIGHT: (C)2008,JPO&INPIT |
