| 摘要 |
PROBLEM TO BE SOLVED: To provide a function verification technique that is more effective in dispensing with test patterns and capable of more effectively reducing the time and cost required to verify functions regarding the design data of a semiconductor device. SOLUTION: Function verification, which is carried out using a plurality of test patterns on the design data of a semiconductor device having a plurality of storage areas and a logic circuit, executes a classification process for comparing partial test patterns except writing process patterns and classifying them into predetermined groups of test patterns; an internal state storage process for specifying reading process patterns included in reference test patterns in each group of test patterns, and storing an internal state corresponding to each of the reading process patterns; an execution procedure setting process for setting, for each group of test patterns, the order of executing the test patterns based on the storage area where the process of reading the test patterns is carried out and on the content stored therein, and for selecting the internal state for use with each test pattern; and a function verification process for performing function verification using the internal state selected. COPYRIGHT: (C)2008,JPO&INPIT
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