发明名称 LAYOUT METHOD OF SEMICONDUCTOR CIRCUIT, PROGRAM, DESIGN SUPPORT SYSTEM
摘要 PROBLEM TO BE SOLVED: To efficiently acquire the layout information of a semiconductor integrated circuit matched with desired circuit characteristics. SOLUTION: This layout method of a semiconductor integrated circuit is provided to acquire transistor characteristic information on the basis of the layout information of a region in which a transistor is formed, and to search a polynomial showing the relation of the characteristic value of the circuit configured of the transistor and the transistor characteristic information, and to calculate a plurality of characteristic values corresponding to the plurality of transistor characteristic information by using the polynomial, and to select part of the plurality of characteristic values on the basis of restriction items relating to the characteristic values, the layout information or the transistor characteristic information, and to acquire the transistor characteristic information or the layout information corresponding to the selected characteristic values. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008117210(A) 申请公布日期 2008.05.22
申请号 JP20060300507 申请日期 2006.11.06
申请人 FUJITSU LTD 发明人 ARIMOTO HIROSHI
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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