| 摘要 |
A system and method for debugging an integrated circuit. According to a preferred embodiment of the present invention, the integrated circuit includes a collection of macros. Each macro further includes a collection of latches controlled by a local clock control. A pattern matcher monitors data patterns in at least one macro. In response to detecting a data pattern indicative of a failure signature within the at least one macro, a check stop logic sends an error detection signal to at least one additional macro and to the local clock control. In response to receiving the error detection signal, the local clock control halts operation with the at least one macro such that data values contributing to said data pattern indicative of said failure signature are retained in the collection of latches. |
