| 摘要 |
A method and a computer system for modeling black box timing of a latch based subsystem are provided to treat efficiently the latch based design by verification of an interface, not internal reverification, when the latch based design is verified at an upper level. A method for modeling black box timing of a latch based subsystem comprises the following several steps. A computer system performs static timing analysis for a circuit, converts a synchronization element and a main IO into nodes, converts a space between the synchronization element and the main IO into an orientation edge according to a signal transfer orientation if an electric signal can be transferred between the synchronization element and the main IO, and performs a weighted graph conversion process for setting a weight, owned by the edge, as a delay taken in signal transfer(S210). The computer system finds an IO pair in a graph obtained in the step of S210 where there is no synchronization element, and constructs a combinational delay arc having a critical path delay between input and output from the found IO pair(S230). The computer system obtains a minimum of values which is resulted from subtraction of the smallest delay to each of adjacent synchronization elements from hold time of the corresponding element, sets the obtained minimum as the hold time for each input, and constructs a hold time arc by using them(S250). The computer system extracts setup time of each input by using an LAT(Latest Arrival Time), and forms a setup time arc by using the extracted setup time(S270). The computer system obtains an IO characteristic curve with respect to all the weakly connected IO pairs on the graph by using an LDT(Latest output Departure Time) and an EDT(Earliest output Departure Time) algorithm(S290).
|
