| 摘要 |
Input/output data transmission between a transmitting integrated circuit and a receiving integrated circuit requires a clock domain synchronizer to synchronize incoming data aligned to a clock signal of the transmitting integrated circuit to a clock signal of the receiving integrated circuit. During a start-up routine, the clock domain synchronizer propagates a pre-determined pattern of data bits through a first circuit path designed to reduce or eliminate metastability. During a normal operations mode, the clock domain synchronizer synchronizes the data signal to the clock signal of the receiving integrated circuit through a second circuit path.
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