发明名称 |
Multi-stack chip size packaging method |
摘要 |
In multi-stack chip size packaging a plurality chips, a first chip is electrically interconnected on a top surface of a substrate using a bump. Next, an epoxy is coated on the first chip and is stacked a second chip thereon, wherein the second chip is electrically interconnected to the substrate through an inner lead bonding. A potting solution is coated on the substrate and the second chip and installed thereon a heat spreader and then cured. An encapsulation resin is coated on a bottom surface of the substrate and electrically interconnected a third chip to the bottom surface of the substrate through a bump and an inner lead bump.
|
申请公布号 |
US7374967(B2) |
申请公布日期 |
2008.05.20 |
申请号 |
US20030747108 |
申请日期 |
2003.12.30 |
申请人 |
DONGBU ELECTRONICS CO., LTD. |
发明人 |
LEE NAEWON |
分类号 |
H01L21/00;H01L23/12;H01L21/98;H01L23/31;H01L23/433;H01L25/065 |
主分类号 |
H01L21/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|