A high resolution time-to-digital converter is provided to reduce power consumption and enhance resolution by using small resistors and resolution control banks. A first delay line(310) includes first resistors which are serially connected. The first delay line receives a first signal through a starting node. A second delay line(320) includes second resistors which are serially connected. The second delay line receives a second signal through a node corresponding to the last node of the first delay line. A plurality of comparators(330) compares first voltages of nodes on the first delay line with second voltages of nodes on the second delay line. An encoder(340) generates digital codes on the outputs of the comparators.
