| 摘要 |
An integrated semiconductor memory includes a memory cell array in which first sense amplifiers are arranged on a right-hand side of the memory cell array and second sense amplifiers are arranged on a left-hand side of the memory cell array. Due to "post-sense coupling" effects upon activation of the sense amplifiers in conjunction with capacitive coupling effects between bit lines, potential changes occur on adjacent bit lines. The integrated semiconductor memory makes it possible to simulate parasitic coupling effects between adjacent bit lines in a functional test in which the first and second sense amplifiers can be activated in temporarily delayed fashion. As a result, the test severity can be improved and test time can be saved.
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