发明名称 CHARGE PUMP CIRCUIT WITH REDUCED PARASITIC CAPACITANCE
摘要 A charge pump circuit is provided with a capacitor for generating a boosted voltage from a power supply voltage in response to a clock signal; and an output node from which the boosted voltage is externally outputted. The capacitor includes a first well formed within a substrate, a second well formed within the first well, first and second diffusion regions formed within the second well to receive the clock signal, a channel region provided between the first and second diffusion regions in which channel region a channel is formed in response to the clock signal; and an electrode positioned over the channel region across a dielectric and connected with the output node. The output node is also connected with the first well to apply said boosted voltage to the first well.
申请公布号 US2008111598(A1) 申请公布日期 2008.05.15
申请号 US20070926704 申请日期 2007.10.29
申请人 NEC ELECTRONICS CORPORATION 发明人 YANAGIGAWA HIROSHI;IDA MASAYUKI;DOI KAZUNORI
分类号 H03L7/06 主分类号 H03L7/06
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