| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a defect tolerance technique for a non-volatile memory device in which a special step is not required, without increasing access time, while suppressing increase in area. <P>SOLUTION: A data processor includes a memory cell MC-R for redundancy and a memory cell MC-C for storing tolerance information that designates a memory cell MC to be replaced with the memory cell MC-R. When the tolerance information is written, the memory cell MC-C is selected by a tolerance bit selection circuit RSEL. The written tolerance information is initially loaded into a tolerance information latch CLAT in accordance with an instruction by a reset signal MD2. In a normal write/read operation, an address comparison circuit ACMP compares the tolerance information with address information supplied from a CPU. When the information match each other, the memory cell MC-R for redundancy is selected. When the information do not match each other, a memory cell is selected in accordance with the address information supplied from the CPU. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
