| 摘要 |
<P>PROBLEM TO BE SOLVED: To detect a phase error with good accuracy even if an amplification level of a read signal varies in a phase error detection circuit and to stabilize the phase synchronization characteristic of a phase locked loop circuit. <P>SOLUTION: The phase error detection circuit 7 includes a computing unit which calculates a ratio Cn (=An/2/Bn) of a sum An and a difference Bn relating to a signal level Xn, X<SB>n-1</SB>in continuous two sampling positions (n), (n-1) of the input signal. The calculation result Cn in the sampling position where the polarities of the signal levels Xn, Xn-1 change is outputted as the phase error signal Tn. Furthermore, the calculated value of An is outputted as the error signal Sn of the input signal DC. <P>COPYRIGHT: (C)2008,JPO&INPIT |
