| 摘要 |
PROBLEM TO BE SOLVED: To provide a frequency-multiplied clock signal output circuit which can output a frequency-multiplied clock signal in a stable state even when the frequency of a clock signal output from a ring oscillator becomes higher. SOLUTION: In a DPLL circuit 1, when the size of a data value which is output from a data latch circuit 52 and should be naturally set in a 11-bit down-counter 54d becomes equal to or more than 12 bits, an overflow preventing circuit 3 substitutes the 11-bit data for the data value. COPYRIGHT: (C)2008,JPO&INPIT
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