| 摘要 |
PROBLEM TO BE SOLVED: To provide a video signal processor capable of constituting a flexibly adaptable digital filter even though a reconfiguration logic of a logically reconfigurable device such as an FPGA (field programmable gate array) is unknown. SOLUTION: The video signal processor is provided with: a shift register 14 for delaying an input video signal; a first coefficient generating means 15 for a video signal; a first product-sum operating means 16 for performing a product-sum operation of a delayed video signal by the shift register 14 and a coefficient by the first coefficient generating means 15; a line memory 19 for storing the video signal from the first product-sum operating means 16; a second coefficient generating means 20 for the stored video signal; and a second product-sum operating means 21 for performing a product-sum operation of the stored video signal and a coefficient by the second coefficient generating means 20, wherein a CPU 6 updates coefficient values of the first and the second coefficient generating means 15 and 20 in accordance with a determined logic of the logically reconfigurable device 4, adjusts the number of required shift register stages and properly controls the supply/the stop of a clock. COPYRIGHT: (C)2008,JPO&INPIT
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