ITERATIVE TEST GENERATION AND DIAGNOSTIC METHOD BASED ON MODELED AND UNMODELED FAULTS

摘要

A diagnostic and characterization tool applicable to structural VLSI designs to address problems associated with fault tester interactive pattern generation and ways of effectively reducing diagnostic test time while achieving greater fail resolution. Empirical fail data drives the creation of adaptive test patterns which localize the fail to a precise location. This process iterates until the necessary localization is achieved. Both fail signatures and associated callouts as well as fail signatures and adaptive patterns are stored in a library to speed diagnostic resolution. The parallel tester application and adaptive test generation provide an efficient use of resources while reducing overall test and diagnostic time.