发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT TECHNIQUE THEREOF
摘要 <p>An internal circuit (151) has timing restrictions only with an internal signal transmitting/receiving circuit (102) but has no timing restrictions with an external signal receiving circuit (101). The external signal receiving circuit (101), therefore, can be laid out without any influences of the timing restrictions of the internal circuit (151). As a result, the external signal receiving circuit (101) can be laid out in such a manner that shortens the distance between the external signal receiving circuit (101) and an external clock terminal (154) and the distance between the external signal receiving circuit (101) and an external data terminal (155), while satisfying timing restrictions existing between the external signal receiving circuit (101) and the external clock terminal (154) or external data terminal (155), whereby timing restrictions occurring between an AC clock signal and an AC data signal can be easily satisfied.</p>
申请公布号 WO2008056468(A1) 申请公布日期 2008.05.15
申请号 WO2007JP64553 申请日期 2007.07.25
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.;NAKAMURA, AKIHIRO 发明人 NAKAMURA, AKIHIRO
分类号 H03K19/0175;G06F1/12;H01L21/82;H01L21/822;H01L27/04 主分类号 H03K19/0175
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