| 摘要 |
A parallel bit test method of a semiconductor memory device is provided to improve current consumption when a number of banks activated at an equal clock signal increases. According to a parallel bit test method of a semiconductor device, a first external command is applied to the semiconductor device. A first internal command generated in response to the first external command is applied to each bank by being dispersed at different transition time of a clock signal. A second external command is applied after the first external command. Data is outputted per each bank through a data pin in response to the second external command.
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