发明名称 |
SYSTEMS AND ARRANGEMENTS FOR CONTROLLING PHASE LOCKED LOOP |
摘要 |
<p>A multi-Gigahertz, low jitter phase locked loop (PLL) with adjustable gain is disclosed. In one embodiment, properties of a f<SUB>Vco</SUB> signal of a PLL can be acquired. Properties can include the occurrences of different types of jitter on the f<SUB>Vco</SUB> signal and the lock status of the PLL. A gain control module can control at least a portion of the PLL based on an analysis of the acquired properties. For example, when the loop is locked or when there is loop filter leakage, the gain of a charge pump in the PLL can be reduced. When a charge pump mismatch is detected based on the acquired properties, additional control signals can be provided to the charge pump to correct the mismatch.</p> |
申请公布号 |
WO2008055755(A1) |
申请公布日期 |
2008.05.15 |
申请号 |
WO2007EP60782 |
申请日期 |
2007.10.10 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION;IBM UNITED KINGDOM LIMITED;CRANFORD, JR, HAYDEN;TOIFL, THOMAS;KOSSEL, MARCEL |
发明人 |
CRANFORD, JR, HAYDEN;TOIFL, THOMAS;KOSSEL, MARCEL |
分类号 |
H03L7/089;H03L7/095;H03L7/10;H03L7/107 |
主分类号 |
H03L7/089 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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