| 摘要 |
A CMOS device with polysilicon protection tiles is shown in FIG. 2 . LOCOS regions 12.1 and 12.2 separate adjacent active regions 16.1 from 16 and 18.1 from 18 , respectively. On the upper surface of the LOCOS regions 12.1, 12.2 are polysilicon tiles 14.1, 14.2 , respectively. At the corner of the gate polysilicon 14.3 and the polysilicon tiles 14.1 and 14.2 are oxide spacers 60.1 - 60.6 . The polysilicon tiles 14.1, 14.2 have silicide layers 50.1, 50.2 . Other silicide layers 50.4 - 50.6 are on the tops of the source, drain and polysilicon gate. An insulation layer 32 covers the substrate and metal contacts 36, 34, 38 extend from the surface of the layer 32 to the silicide layers on the source, gate and drain, respectively. The polysilicon tiles are made from the same layer of polysilicon as the gate and they are formed simultaneously with the gates. The intention of the polysilicon tiles is to reduce erosion of the field oxide between closely spaced active regions. In addition, the poly tiles themselves increase the thickness of the isolation between active silicon regions when it must serve as a self-aligned blocking layer for an ion implantation step.
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