| 摘要 |
<p>A block cipher device (10) for a cryptographically secured digital communication system includes a pair of first stages (16a, 16b) connected in parallel for receiving an input data block (XIN) and a control data block (Z1a, Z1b). Each first stage (16a, 16b) defines a respective first data path and includes a sum modulo-two unit (40a, 40b) for receiving the control data block (Z1a, Z1b) and the input data block (XIN) . Each first stage (16a, 16b) also includes a first nibble swap unit (42a, 42b) downstream from the sum modulo-two unit (40a, 40b). A key scheduler (18) generates a random key data block based upon a received key data block. A pair of second stages (20a, 20b) is connected in parallel downstream from the first stages (16a, 16b) and receives the random key data block, the control data block (Z1a, Z1b) and output signals (W1a, W1b) from the first stages (16a, 16b) for providing an output data block (YOUT). Each second stage (20a, 20b) defines a respective second data path and includes a plurality of modulo units. The block cipher device (10) further includes a bit diffuser (22) connected in both of the first data paths for mixing data therebetween. <IMAGE></p> |
