发明名称 Method and apparatus for verifying a site-dependent wafer
摘要 The present invention includes a method of verifying a Site-Dependent (S-D) wafer that includes receiving a first set of S-D wafers by one or more S-D processing elements in one or more processing subsystems, creating a first set of unverified S-D wafers by performing a first S-D creation procedure, establishing S-D wafer state data for each unverified S-D wafer, establishing a first set of evaluation wafers comprising a first number of the unverified S-D wafers, establishing first operational states for a plurality of S-D evaluation elements, determining a first number of available evaluation elements, establishing a first S-D transfer sequence, transferring the first set of S-D evaluation wafers to the first number of available evaluation elements in one or more evaluation subsystems and applying a first corrective action when the number of S-D evaluation wafers is greater than the first number of available evaluation elements.
申请公布号 US7373216(B1) 申请公布日期 2008.05.13
申请号 US20070730283 申请日期 2007.03.30
申请人 TOKYO ELECTRON LIMITED 发明人 WINKLER MARK;WINTER THOMAS
分类号 G06F19/00 主分类号 G06F19/00
代理机构 代理人
主权项
地址