METHODS OF FABRICATING SEMICONDUCTOR DEVICE HAVING MOS TRANSISTORS WITH GATE INSULATOR LAYER OF DIFFERENT THICKNESSES

摘要

A method for fabricating a semiconductor device having MOS transistors including gate insulation layers of different thicknesses is provided to reduce three photolithography processes into one photolithography process by forming an align key by a mask pattern fabricated in one photolithography process while an isolation layer recessing process is performed. A semiconductor substrate(1) is prepared which has a cell region(C) and a peripheral circuit region(P). An isolation layer is formed in the semiconductor substrate to confine a cell activation region(5c) and a peripheral circuit activation region(5p). A buffer oxide layer is formed on the resultant structure. Impurity ions are implanted into the substrate to form a well. The buffer oxide layer is removed. A first gate insulation layer(15) is formed on the resultant structure. A mask pattern(20) is formed on the resultant structure, including an opening exposing the cell region. While the first gate insulation layer in the cell region is removed by using the mask pattern as an etch mask, the isolation layer is recessed to expose a part of the sidewall of the cell activation region. The mask pattern is removed. A second gate insulation layer is formed on the resultant structure. A cell gate electrode and a peripheral circuit gate electrode are formed on the resultant structure.